Technological Advancements To Improve Silicon Carbide Substrate CMP Efficiency
With the continuous progress of semiconductor technology, silicon carbide (SiC), as a high-performance material, has shown great application potential in the field of power electronic devices. However, in the preparation process of silicon carbide substrate , surface quality control is particularly critical, especially after thinning, grinding and polishing and other processes to obtain ultra-smooth surface. Among them, chemical mechanical polishing (CMP), as one of the key steps, is of great significance for removing the damaged layer left by the previous process and achieving high surface levelling. However, the traditional CMP process faces the problem of low material removal rate (MRR), which directly affects the production efficiency and cost. Therefore, exploring new technologies to improve the CMP efficiency of SiC substrate has become the focus of current research. 1. Basic principles and challenges of SiC substrate CMP The surface damage depth of the thinned or ground Si